PROCESSORS USED IN ALACRON PRODUCTS

The Nexperia VLIW Microprocessors

Alacron's FastSeries family of processor and multiprocessor boards is based on the Nexperia family of Very Long Instruction Word (VLIW) microprocessors.
Alacron’s FastSeries Family includes:

  • FastX1703: A raw-length 4xPCIe board with a Xilinx Vitex5 LXT FPGA and up to four Nexperia PNX1702 or PNX1502 processors, each with 64 MB of dedicated high speed DDRAM. Input options include six Camera links, LVDS, UXGA, or analog. Each board has capability of providing over 10 GFLOPS of computational power
  • FastImage1303: A full-length PCI board with up to four Nexperia PNX1302 processors, each with 8–16 MB of dedicated high speed (572 MB/sec) SDRAM and the capability of providing over 2.6-3.6 GFLOPS of computational power
  • FastFrame1303: A PCI framegrabber available in both analog/digital and digital-only configurations for greater flexibility and cost savings
  • FastVault-FL: A VME form factor frame grabber and high speed flash storage device available in both sFPDF, GigE, and Camera (channel) Link configurations for greater flexibility and cost savings.
  • Fast4: A PMC board that expands the FastImage1303 PCI Board with up to eight additional Nexperia processors
  • FastI/O: A PMC daughter-card that lets you add extra I/O ports to your FastImage or FastFrame PCI board


Philips Semiconductors (an affiliate of Royal Philips Electronics), building on award-winning TriMedia™ (very-long instruction word) VLIW processor technologies, creates and license new VLIW processor cores and sophisticated software tools and applications for advanced digital consumer products. Examples of these products include digital televisions, advanced set-top boxes, personal video recorders, video editing systems, home networking devices, security and surveillance systems, and videophones.By incorporating the Nexperia processor into Alacron’s FastSeries Family, customers and developers can significantly increase their processing power enabling them to work more efficiently and cost effectively.

PNX1302 NEXPERIA PROCESSOR

Continuing a tradition of high-performance, low-cost media processors, the Philips Nexperia (formerly TriMedia™) PNX1302 delivers more processing power to multimedia applications at a lower unit cost. The PNX1302 boosts performance through a faster clock speed and a faster main memory interface than previous Nexperia (TriMedia) processors. Datastream I/O is enhanced with a new on-chip unit for handling audio output in Sony/Philips digital format (SPDIF). Lower power consumption and a smaller footprint contribute to making the PNX1302 a more efficient and compact processing solution.

PNX1302 Features

  • Processes audio, video, graphics and communications data-streams on a single chip
  • Ideal for video-centric multimedia applications
  • Powerful, fine-grain parallel, 180-200MHz VLIW CPU
  • Versatile instruction set includes traditional microprocessor, special multimedia SIMD, and IEEE floating-point operations
  • Comprehensive software development tools enable multimedia application development entirely in the C/C++ programming languages
  • On-chip, independent, DMA-driven multimedia I/O and coprocessing units offload the CPU
  • PCI/XIO host bus interface supports glueless interface to PCI and eight-bit microcomputer peripherals, including ROM/Flash, EEPROM, 68K, and x86 devices
  • 16- and 64-Mbit SDRAM support up to 143 MHz
  • On-chip DVD playback authentication/descrambling
  • Application libraries available from Philips and third-party suppliers provide solutions for MPEG-2 decode, Dolby Digital (AC-3) ® decode, and more


Block Diagram


About VLIW

  • Very Long Instruction Word (VLIW) Architecture
  • Fine-grain parallel
  • Optimize parallelism at compile time, not during execution
  • 5-issue slot engine
  • 27 pipelined functional units
  • No special scheduling logic required
  • Executes up to 5 operations per clock cycle
  • Breakthrough scheduling compile

Click here to Download DataSheet or here to Download Data Book

PNX1502 NEXPERIA PROCESSOR

Introduction

The PNX1500 leverages a powerful, completely redesigned C/C++ programmable TriMedia TM3260 CPU for improved media processing.
It runs a small real-time operating system enabling efficient and predictable response to real-time events. Independent, on-chip, bus- mastering DMA units capture and format datastream I/O and accel- erate processing of multimedia algorithms. A sophisticated memory hierarchy manages internal I/O and streamlines access to external memory. The result—a low-cost, programmable media processor proven in standalone and hosted multimedia products.

C/C++-programmable VLIW CPU


The PNX1500 CPU core delivers top performance through an elegant implementation of a fine-grain parallel very-long instruction word (VLIW) architecture. Five issue slots enable up to five simultaneous RISC-like operations to be scheduled into only one VLIW instruction. These operations can simultaneously target any five of the CPU's 31 pipelined functional units within one clock cycle.

Block Diagram

Click here to Download DataSheet or here to Download the Manual

PNX1702 NEXPERIA PROCESSOR

Introduction

The PNX1700 leverages a powerful, completely redesigned C/C++ programmable TriMedia TM3260 CPU for improved media processing.
It runs a small real-time operating system enabling efficient and predictable response to real-time events. Independent, on-chip, bus- mastering DMA units capture and format datastream I/O and accel- erate processing of multimedia algorithms. A sophisticated memory hierarchy manages internal I/O and streamlines access to external memory. The result—a low-cost, programmable media processor proven in standalone and hosted multimedia products.

C/C++-programmable VLIW CPU


The PNX1700 CPU core delivers top performance through an elegant implementation of a fine-grain parallel very-long instruction word (VLIW) architecture. Five issue slots enable up to five simultaneous RISC-like operations to be scheduled into only one VLIW instruction. These operations can simultaneously target any five of the CPU's 31 pipelined functional units within one clock cycle.

Block Diagram

Click here to Download DataSheet or here to Download the Manual