The Fast-VIDEO2 is a performance frame grabber for analog signals. The board is capable of simultaneously digitizing two independent UXGA sources without multiplexing and four with multiplexing. The data can be processed in real-time using a Xilinx FPGA or the 440GP PowerPC processor. The output can either be an optional UXGA display RAMDAC and/or the PCI-X bus. This board is a reduced performance and cost version of the Fast-UXGA-4 which is ideal for a wide range cost sensitive applications.
Block Diagram of the Hardware
The Hardware consists of a PCI raw form-factor PCI-X interface board with the following major functional units as shown on the diagram below.
The functional units are:
- UXGA input X2
- Programmable FPGA
- UXVGA output (optional)
- 440GP PowerPC processor (optional)
- PCI-X interface
Click below to Download DataSheet
IBM 440GP Datasheet ( 241 KB)
IBM 440GP programming Overview ( 87 KB)
The major programmable units are the FPGA and the 440GP/PCI-X interface DMA engine. The FPGA and Software API for the functionality of the driver are presented below.
Host Software API
API Block Diagrams
The API provides configuration and control access to one or more FAST-UXGA boards. There is no specific limitation to the number of boards the software can support, though the number of slots in the computer imposes a practical limit.
The API supports enumeration of the boards, and the creation of ‘configurations’, which determine the settings for all the boards in the system.
Multiple configurations can be defined, and then later selected by a single API call. This provides for switching modes as quickly as the hardware supports, typically one frame time for synchronized video, two frame times for asynchronous input video.
In addition the API provides for the allocation and management of shared memory buffers. A single buffer may be shared by many boards, allowing the DMA engine on each board to place its output in an image of larger scope then that produced by a single board.
The API provides essentially two interfaces, a vcConfig interface for passing data to the FAST-UXGA subsystem, and a vcInquire interface for obtaining non-video- information from the API.
These two methods have two parameters, a type parameter which defines the type of data being pointed to by the second parameter, a void pointer. The void pointer points to types, which are filled in by the API call, or by the user, to perform the function selected by the type parameter.
Video data is passed in shared memory buffers allocated by the API for use by the host and the boards. In order to setup a buffer in host memory a vcConfig call is made after the user fills out a vcBuffer_t with the desired shape of the buffer. Double (or more) buffering is supported by setting nBuffers in the vcBuffer_t to larger than one. In that case the use must call vcInquire (vcInquireImageBufferLocation,...) in his callback function to determine which buffer was just completed. You may use a single memory buffer, but the buffer will be updated by the board(s), at the same time you access it. Multiple boards and configurations can use a particular shared memory buffer. If more than one buffer is allocated by a call then the buffers are used in a circular fashion.
Notifications of image updates may be obtained by registering a call back function with the API. This is not required however, image data will be updated in memory as fast as the system allows, and the frame rate of the sources allow. If multiple buffers (nBuffers > 1) are used it probably makes sense to provide a callback function so that you can determine the order of buffer updates.
When the vcInit method is called the number of boards in the system enumerated. The host application can inquire about how many boards are detected with the vcInquire API (vcInquire(vcInquireBoards,..)).
The API supports up to 8 configurations, which are delineated by the ConfigNumber field in the structures used to define a configuration. A particular configuration number applies across all the boards. When it is selected (vcConfig(vcConfigSelect,..)) the state of all the boards is updated to use the selected configuration. Typically a particular portion of a configuration is stored local to each board in DDR SDRAM, and the select operation just writes the base address register in all the FPGA's on all the boards.
Combined image data is DMA-ed into host memory by the PLX-9656 on each board. The DMA is a two dimensional DMA, in that a stride, offset, number of columns, and number of rows is provided in the hardware for each DMA. This allows images from multiple boards to be combined in memory into a larger image, by re-using a buffer number across multiple boards in a configuration.